Authors
Virendra Sharma
Abstract
Indian mathematics has an ancient technologies that is ‘Vedic mathematics’ which as an exclusive system of calculations which depends on simple principles and rules which have 16 Formulae (Sutras). This paper discusses about A high speed complex multiplier design (ASIC) that is Vedic Mathematics. From earliest Indian mathematics “Vedas”, adopted the knowledge for planning adder subtractor and multiplier unit. In which, multiplication is a significant factor in mathematics action which is used in number of Digital Signal Processing applications. For execution, the phenomenon of multiplication takes more time, so there is a need of quick multiplier for saving performance time. This paper, discuss about the multiplication using Earliest Indian Vedic Mathematics procedures. In techniques, describes the Urdhva Tiryakbhyam, Nikhilam Sutra, and Karatsuba-of man and technique is obtained from performance analysis due to which solving a whole range mathematical problems by its high speed. It also discuss about the convolution that is an official mathematical process, just as addition, multiplication and integration. Keywords: Complex Multiplier, Vedic Mathematics, Convolution, A high speed complex multiplier design (ASIC)
Introduction
In arithmetic operations, Complex Multiplication is a significant and enormous purpose in Digital Signal Processing (DSP) and Image Processing (IP). Through the use of two addition/ subtractions and four real number multiplications execute the Complex number multiplication. It is necessary to circulate to most significant bit (MSB) from least significant bit (LSB) in real number processing in case of binary partial products added. After binary multiplications, addition and subtraction limit the overall speed. Multiply and Accumulate (MAC) is Multiplication-based operations and internal produce are between some of the frequently used Computation- Intensive Arithmetic Functions (CIAF) presently performed in several Digital Signal Processing (DSP) that have uses like Fast Fourier Transform (FFT), convolution, cleaning and in microchips in its logic and arithmetic unit. Multiplication controls the performance time of most DSP procedures, so its necessity of high speed multiplier. In determining the tutoring cycle period of DSP chip, multiplication period is still central factor.
As a result of increasing computer and signal treating requests, demand has been increase for processing of high speed. In several image processing application and real-time signal, advanced quantity mathematics processes are significant to attain preferred performance. Multiplication is one of the most significant arithmetic operations and expansion of fast multiplier route has been a topic of attention over periods. Multiplier depends on Vedic Math, fastest and low power multiplier. It is the processor design’s building blocks and also known as DSP’s heart. The speed of computation of Current multipliers are decrease as the input data increase. Today, many multipliers are available such as array multiplier, combinational multiplier, sequential and parallel multiplier and others. By using Vedic math, building high speed multipliers for processor project is done. Filtering is generally used in DSPs and in numerous applications such as speech processing etc. In DSP, digital multiplier are most commonly used components such as reliable, fast and effective that are used to apply any operation.
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| APA Style | Sharma. V (2019). Multiplication Techniques used in Vedic Mathematics. Academic Journal of Mathematical Sciences, 1(1), 7-12 |
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